Structured Computer Organization(6th Edition)

Structured Computer Organization(6th Edition)

作者: 
Andrew S. Tanenbaum / Todd Austin
语言: 
ISBN: 
9780132916523
出版日期: 
星期三, 八月 1, 2012

简介

Structured Computer Organization, specifically written for undergraduate students, is a best-selling guide that provides an accessible introduction to computer hardware and architecture. This text will also serve as a useful resource for all computer professionals and engineers who need an overview or introduction to computer architecture.
This book takes a modern structured, layered approach to understanding computer systems. It's highly accessible - and it's been thoroughly updated to reflect today's most critical new technologies and the latest developments in computer organization and architecture. Tanenbaum’s renowned writing style and painstaking research make this one of the most accessible and accurate books available, maintaining the author’s popular method of presenting a computer as a series of layers, each one built upon the ones below it, and understandable as a separate entity.

目录

PREFACE
1 INTRODUCTION
1.1 STRUCTURED COMPUTER ORGANIZATION
1.2 MILESTONES IN COMPUTER ARCHITECTURE
1.3 THE COMPUTER ZOO
1.4 EXAMPLE COMPUTER FAMILIES
1.5 METRIC UNITS
1.6 OUTLINE OF THIS BOOK
2 COMPUTER SYSTEMS
2.1 PROCESSORS
2.2 PRIMARY MEMORY
2.3 SECONDARY MEMORY
2.4 INPUT/OUTPUT
2.5 SUMMARY
3 THE DIGITAL LOGIC LEVEL
3.1 GATES AND BOOLEAN ALGEBRA
3.2 BASIC DIGITAL LOGIC CIRCUITS
3.3 MEMORY
3.4 CPU CHIPS AND BUSES
3.5 EXAMPLE CPU CHIPS
3.6 EXAMPLE BUSES
3.7 INTERFACING
3.8 SUMMARY
4 THE MICROARCHITECTURE LEVEL
4.1 AN EXAMPLE MICROARCHITECTURE
4.2 AN EXAMPLE ISA: IJVM
4.3 AN EXAMPLE IMPLEMENTATION
4.4 DESIGN OF THE MICROARCHITECTURE LEVEL
4.5 IMPROVING PERFORMANCE
4.6 EXAMPLES OF THE MICROARCHITECTURE LEVEL
4.7 COMPARISON OF THE I7, OMAP4430, AND ATMEGA168
4.8 SUMMARY
5 THE INSTRUCTION SET
5.1 OVERVIEW OF THE ISA LEVEL
5.2 DATA TYPES
5.3 INSTRUCTION FORMATS
5.4 ADDRESSING
5.5 INSTRUCTION TYPES
5.6 FLOW OF CONTROL
5.7 A DETAILED EXAMPLE: THE TOWERS OF HANOI
5.8 THE IA-64 ARCHITECTURE AND THE ITANIUM
5.9 SUMMARY
6 THE OPERATING SYSTEM
6.1 VIRTUAL MEMORY
6.2 HARDWARE VIRTUALIZATION
6.3 OSM-LEVEL I/O INSTRUCTIONS
6.4 OSM-LEVEL INSTRUCTIONS FOR PARALLEL PROCESSING
6.5 EXAMPLE OPERATING SYSTEMS
6.6 SUMMARY
7 THE ASSEMBLY LANGUAGE LEVEL
7.1 INTRODUCTION TO ASSEMBLY LANGUAGE
7.2 MACROS
7.3 THE ASSEMBLY PROCESS
7.4 LINKING AND LOADING
7.5 SUMMARY
8 PARALLEL COMPUTER ARCHITECTURES
8.1 ON-CHIP PARALELLISM
8.2 COPROCESSORS
8.3 SHARED-MEMORY MULTIPROCESSORS
8.4 MESSAGE-PASSING MULTICOMPUTERS
8.5 GRID COMPUTING
8.6 SUMMARY
9 BIBLIOGRAPHY
A BINARY NUMBERS
A.1 FINITE-PRECISION NUMBERS
A.2 RADIX NUMBER SYSTEMS
A.3 CONVERSION FROM ONE RADIX TO ANOTHER
A.4 NEGATIVE BINARY NUMBERS
A.5 BINARY ARITHMETIC
B FLOATING-POINT NUMBERS
B.1 PRINCIPLES OF FLOATING POINT
B.2 IEEE FLOATING-POINT STANDARD
C ASSEMBLY LANGUAGE PROGRAMMING
C.1 OVERVIEW
C.2 THE 8088 PROCESSOR
C.3 MEMORY AND ADDRESSING
C.4 THE 8088 INSTRUCTION SET
C.5 THE ASSEMBLER
C.6 THE TRACER
C.7 GETTING STARTED
C.8 EXAMPLES
INDEX